1. Field of the Invention
The present invention relates to a charge pump, and more particularly, the present invention relates to a differential charge pump capable of correction.
2. Description of Related Art
A phase lock loop (PLL) circuit is directed to a circuit system, which can produce a signal with the phase and frequency being fixed at a base. It has always been a difficult issue for the manufacturers to produce a phase lock loop circuit with low noise level and fast operation.
Referring to FIG. 1, it shows a circuit block diagram, schematically illustrating a conventional phase lock loop circuit 100. The phase lock loop circuit 100 includes a phase/frequency detector (PFD) 102, a loop filter (LP) 104, a voltage controlled oscillator (VCO) 106, and a frequency divider 108. The phase/frequency detector 102 can receive an input frequency fIF and a reference frequency fref simultaneously. Also, according to a phase difference between the two frequencies, the phase/frequency detector 102 exports an output signal SI to the loop filter 104. The loop filter 104 is used to filter out the undesired noise and then export a signal SO, which is inputted to a VCO 106. The output frequency fOF outputted from the voltage control oscillator 106 is used as an output for the phase lock loop circuit 100. In addition, the output frequency fOF is further inputted to a frequency divider 108. The reference frequency fref outputted by the frequency divider 108 is equal to an output frequency fOF divided by a positive integer N, in which the quantity of N is determined by the control signal fCO that is inputted to the frequency divider 108.
After the phase lock loop circuit 100 is activated and after a settle time period, the phase lock loop circuit 100 then enters a phase lock state. At this moment, the reference frequency fref is equal to the input frequency fIF, and the output frequency fOF then is equal to N×fref.
A post stage circuit of the phase/frequency detector 102 is a charge pump circuit. Referring to FIG. 2, it shows a circuit diagram, schematically illustrating a conventional charge pump circuit. The charge pump circuit 200 is composed of two current sources IUP and IDN, and a number of switching devices S1, S2, S1′, and S2′. The node connecting the switching devices S1′ and S2′ is coupled to a reference VR. When the switching device S1 receives a rising signal fp from the previous stage of the circuit (that is the ON state), it will cause the charge pump 200 to export a rising current. When the switching device S2 receives a falling signal fd from the previous stage of the circuit, it will cause the charge pump 200 to export a falling current. The state of the switching device S1′ is the inverse of the state of the switching device S1, and the state of the switching device S2′ is the inverse of the state of the switching device S2. When the switching devices S1 and S2 are both in an open circuit, which is the OFF state, the switching devices S1′ and S2′ are at the ON state, so as to prevent the current source IUP and IDN from floating. The rising signal fp and the falling signal fd are determined according to the phase difference between the reference frequency fref and the input frequency fIF.
Theoretically, the charge pump has two current sources IUP and IDN, of which the physical properties of the circuit elements are the same. In other words, the current level exported by the current source IUP and the current level exported by the current source IDN are the same. However, in the practical situation, the two current sources may not be the same due to errors in the fabrication process or the differences in the properties of the circuit elements. For these reasons, when the charge pump 200 receives the same rising and falling signals fp and fd, the actual levels of current outputted are not the same. At this moment, even if the phases between the reference frequency fref and the input frequency fIF are the same, the phase current Io exported from the charge pump is not zero. In this situation, the effect of phase lock for the phase lock loop circuit would worsen.
Conventionally, correction of this error in the charge pump is done by various methods. For further description, the conventional differential charge pump is taken as an example. Referring to FIG. 3, it shows a circuit diagram, schematically illustrating the conventional differential charge pump 300. The differential charge pump 300 includes a first charge pump 310, a second charge pump 320, and a common mode feedback device CMP, so as to export a current to cause the capacitor C to charge or discharge, where the capacitor C is a front stage of circuit in the loop filter 104. The first charge pump 310 includes a current source IUP1, a current source IDN1, and a number of switching devices S1, S2, S1′, and S2′, in which the coupling relation is as shown in FIG. 3. The switching device S1 is controlled by the rising signal fp; the switching device S2 is controlled by the falling signal fd; and the switching device S1′ and the switching device S2′ are respectively inverse to the switching device S1 and the switching device S2. The node A is the output terminal of the first charge pump 310, and the node A′ is the terminal for receiving a first reference voltage VR1. The second charge pump 320 includes a current source IUP2, a current source IDN2, and a number of switching devices S3, S4, S3′, and S4′, in which the coupling relation is as shown in FIG. 3. The switching device S4 is controlled by the rising signal fp; the switching device S3 is controlled by the falling signal fd; and the switching device S3′ and the switching device S4′ are respectively inverse to the switching device S3 and the switching device S4. The node B is the output terminal of the second charge pump 320, and the node B′ is the terminal for receiving the first reference voltage VR1. The two terminals of the capacitor C are electrically coupled with the node A and node B respectively.
When the differential charge pump 300 receives the rising signal fp, the switching device S1 and the switching device S4 are conducted to each other. The current exported by the charge pump 300 flows through the capacitor C via the switching device S1 and the node A, and also through the switching device S4 and the current source IDN2, so as to charge the capacitor C. When the differential charge pump 300 receives the falling signal fd, the switching device S2 and the switching device S3 are conducted to each other. The current exported by the charge pump 300 flows through the capacitor C via the switching device S3 and the node B, and also through the node A, the switching device S2, and the current source IDN1, so as to discharge the capacitor C. The averaged voltage for the nodes A and B is the common mode voltage. The common mode feedback device CMP is used to receive the voltages from the node A and the node B as well as the second reference voltage VR2, and to compare the averaged voltage between the node A and node B with the second reference voltage VR2, so as to accordingly export an adjusting signal Vf for adjusting the quantities of the current sources IUP1 and IUP2. The differential charge pump has the following disadvantages:
1. Since it includes two sets of charge pumps, the circuitry is very complicated.
2. It can only assure that IUP1+IUP2=IDN1+IDN2. It cannot assure that IUP1=IUP2 and IDN1=IDN2.
3. When the differential charge pump 300 is idle for a long period (that is, the switching device S1, S2, S3, and S4 are all in open circuit) the capacitor C is floating and the common mode voltage would likely shift.